Abstract: Since the dawn of AI/ML capabilities, the software industry has pivoted from analyzing massive amounts of data to creating sophisticated models, capable of analysis and artificial intelligence that drives the architecture solutions from both Si and advanced packaging platform. While Moore’s law has continued to yield transistor scaling necessary for these applications, both compute and memory bandwidth have lagged the ever growing demand from models for AI training and inference, an ask that Silicon scaling cannot address on its own. In sharp contrast to the past, the advent of advanced interconnects has resulted in a unique position for packaging. Advanced packaging is driving Moore’s law by leading system performance and definition via disaggregation and reaggregation of chips at an increasingly finer granularity. Such schemes yield impressive results by combining Chips, Chiplets and advanced interconnects in novel architectures that push the system envelope to deliver aggressive compute and memory bandwidths.
We will discuss with examples, the challenges of utilizing packaging elements to their full potential and discuss how co-optimization is crucial to achieving the best results for any given set of system requirements and constraints.