2026 Tutorials
Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlighted Papers | Invited Speakers
Tutorial Program at a glance
List of Tutorials
TUT1: Reliability Challenges in 3DIC Packaging
Sherwin Tang (TSMC)
This tutorial provides an overview of semiconductor industry's achievement, introduces TSMC's 3D Fabric advanced system integration which consists of CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated Fan-Out), and SoIC (System-on-Integrated-Chip), discusses reliability challenges and failure modes in advanced packaging, and reviews methdologies (measurement, charaterization, and modeling) accompanied by case studies.
Sherwin Tang is a Senior Technical Manager in the Quality and Reliability Organization of TSMC. He has over 30 years of industrial experience including foundry and IDM companies. At TSMC, his recent contributions have focused on driving advancements in reliability stress methodologies for cutting-edge silicon nodes, particularly to address challenges in packaging interaction. By collaborating with internal partner organizations, he has successfully developed innovative solutions to mitigate FBEOL (Far-Backend-of-Line) related delamination and cracking issues in advanced silicon nodes and achieved the adoption of his proposed new FBEOL process flow that enhances robustness and reliability. Furthermore, his work has delivered integrated solutions that support the continued evolution of 3DIC packaging technologies. Sherwin holds a Ph.D. from Missouri University of Science and Technology where his research was electrochemistry of metal and plasma enhanced CVD process.
TUT2: A Review of Reliability in GaN Power HEMTs
Matteo Borga (IMEC)
This tutorial examines the main reliability aspects of GaN power HEMTs, focusing on key device elements such as buffer layers and gate structures. It outlines mechanisms that limit device reliability and stability, along with dynamic behavior and trapping effects, their characterization, and impact on the device performance. It will provide a concise perspective on principles essential for ensuring efficient and reliable operation in advanced GaN power electronics.
Matteo Borga is an R&D Engineer at imec, specialized in GaN power electronics with strong expertise in device physics, reliability, and advanced electrical characterization of power semiconductors. Matteo earned a Master’s degree in Electronic Engineering from the University of Padova in 2016 and completed a Ph.D. in Information Engineering at the same university in 2020. During the Ph.D., Matteo focused on reliability characterization of GaN power devices, including HEMTs and vertical MOSFETs.
Currently, Matteo’s work centers on advancing lateral HEMT device technology across a broad range of application voltages and contributing to the development of vertical GaN MOSFET devices. This involves integrating device design, physics-based modeling, and advanced electrical characterization to gain deep insights into the physical mechanisms that limit device performance and reliability, enabling improvements in both architecture and process optimization.
TUT3: Resistive Random Access Memory for High Density Storage and Computing Applications
Daphne Chen (Ying-Chen) (Arizona State University)
This tutorial provides an overview of resistive random-access memory (RRAM) as a next-generation memory solution, highlighting its high scalability, low power consumption, fast switching speed, and strong potential for future in-memory computing. We will explore both linear and nonlinear RRAM devices enabled by oxide thin films, microstructural modulation, and low-dimensional heterogeneous integration. Specific focuses will include the reliability challenges on 1R-only RRAM configuration, where intrinsic nonlinearity facilitates scalable, energy-efficient, high-density storage, and high-performance computing applications.
Dr. Daphne Chen received a Ph.D. in Electrical and Computer Engineering from The University of Texas at Austin in 2019. She is currently an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. Prior to joining ASU, she was an R&D Emerging Memory Engineer in the path-finding group at Micron Technology, where she contributed to the development of next-generation memory solutions. At ASU’s Semiconductor Device Research Laboratory (SDRL), her research focuses on materials for emerging devices, physical modeling, novel computing paradigms, hardware security, and energy-efficient computational architectures—particularly focusing on back-end-of-line (BEOL) compatible integration for future electronics. She holds 3 U.S. patents, involved in 4 books, and has authored over 80 research papers published in international journals and conferences on the topics of emerging memory technologies and semiconductor devices.
TUT4: Reliability and Test of System-in-Package Semiconductors in the AI Era
Mehul Shroff (NXP)
Modern semiconductor products support various applications, diverse functionality, and increased performance and reliability requirements, resulting in technology scaling to ever-shrinking dimensions with novel materials, device architectures, and packaging. As a result, the industry is moving to a system-in-package approach. Comprehensive, cost-efficient testing is necessary to minimize escapes. Reliability requirements necessitate collaboration among various stakeholders. This talk will explore key considerations, including machine learning and artificial intelligence, for system-in-package reliability and test, to ensure successful products.
Mehul Shroff is a Fellow and Six Sigma Black Belt at NXP Semiconductors in Austin, TX, USA, with over 30 years of experience in the semiconductor industry. His current interests are focused on reliability tools and methodologies, design for reliability, and data science and machine learning for quality and reliability. His prior experience includes process integration and device engineering in manufacturing, technology transfer, and development, module development, yield engineering, and test vehicles and test structures. He holds graduate degrees in Chemical Engineering and Software Engineering.
TUT5: Radiation Effects in GaN
Tania Roy (Duke University)
Dr. Tania Roy is an Associate Professor in the Department of Electrical and Computer Engineering at Duke University. Prior to joining Duke in 2023, she was a faculty at University of Central Florida from 2016 to 2022. Her current research interests lie in developing hardware for artificial intelligence applications using novel functional materials including two-dimensional materials. She works on radiation effects and reliability of GaN, and the development of materials beyond silicon, such as amorphous oxide semiconductors and 2D materials. She won the PECASE award in 2025, NSF CAREER award in 2019, UCF Luminary award in 2021. She was nominated as a “Rising Star in EECS” in 2014. She is a core organizer of premier conferences in her research area, serving as the Technical Program Chair of Device Research Conference and the Emerging Device and Compute Technology subcommittee chair of IEDM. She is also an Associate Editor of NPJ 2D Materials and Applications. Roy was a postdoctoral researcher at University of California, Berkeley and Georgia Institute of Technology. She obtained her PhD and MS degree in Electrical Engineering from Vanderbilt University.
TUT6: X-ray Microbeam Techniques for Probing Stress Induced Phenomena in Interconnects
Ping-Chuan Wang (SUNY New Paltz)
TUT7: Data Center Resiliency
Sanjay Gongalore (NVIDIA)
TUT8: Introduction to SiC power MOSFET technology and reliability
Peter Moens (onsemi)
This tutorial provides the audience with insight into the reliability status of SiC power devices. The following topics will be addressed: Characterization of the SiC/SiO2 interface by charge pumping and ultra-fast BTI measurements Identification of the physical nature of the interface point defects through electrically detected magnetic resonance Gate Switching instability Gate oxide reliability (TDDB) and lifetime. Comparison of SiC/SiO2 to Si/SiO2Reverse bias reliability Cosmic ray susceptibility Short circuit withstanding time Bipolar degradation.
Peter Moens received a Master in nuclear physics and a Ph.D. in solid state physics from the University of Gent, Belgium, in 1990 and 1993 respectively. At onsemi he was responsible for the development of 600+V GaN based power devices (2009-2019). Since 2019, he is working on SiC MOSFETs. He is/was a member of the technical program committees of IEDM, ISPSD, IRPS, CSMANTECH, ICSCRM, IRW, EDTM, ESSDERC and ESREF. He was the General chair of ISPSD 2012. He authored and co-authored over 200 publications in peer reviewed journals or conferences, 20 invited papers, and is the recipient of 6 best paper awards (including 2 ISPSD best paper awards as first author). He presented tutorials on smart power reliability and GaN power device reliability at IRPS and ISPSD and contributed to 2 books chapters on GaN power devices and reliability. He is an inductee of the ISPSD International Hall of Fame. He holds 62 US patents.
TUT9: BEOL
Huai Huang (IBM)
TUT10: What Can In-System Test and SLM Data Bring to the Reliability Community
Adam Cron (Synopsys)
We will first explain foundational DFT concepts like DFT, ATPG, BIST, and IFS; then review other sources of systemic data like sensors and monitors. Next, we will take a brief look at how to extract these sources of information and use them in-system or for fleet monitoring, focusing on both SLM and DFT data sources. Lastly, we will look at a few case studies (e.g., cell characterization, and reliability prediction) and future trends.
Adam Cron is a Distinguished Architect at Synopsys working with customers worldwide on complex Test, Security, and Silicon Lifecycle Management tool flows and architectures for digital ICs. He has helped architect design-for-test, design-for-manufacturing, and security tools for several generations of products. As a Syracuse University Computer Engineering graduate, Adam also worked in test-related fields at Motorola and Texas Instruments where he got his first exposure to IEEE standards while designing the first ICs compliant to IEEE Std 1149.1. In the past, Adam has served as Chair or Vice-chair of the Test Technology Standards Committee overseeing the development of IEEE Test Standards for about a dozen years. Adam is Chair of IEEE Std 1838 which standardized 3D-IC test access; Editor of IEEE Std 1149.4 for a mixed-signal test bus; a member on many IEEE Test Standards working groups such as P1687, P1687.2, P2929, and P3405; an IEEE Golden Core recipient for long-standing service to the society; and recipient of the 2024 IEEE CS Hans Karlsson Standards Award, and the recipient of the 2025 IEEE SA Lifetime Achievement Award “for continuous and outstanding service to the standards development community in the field of electronic testing and design-for-test solutions.” He has authored several papers, articles, book chapters, and patents and is a frequent speaker or panelist at conference sessions held at events such as ITC and DAC.
TUT11: Radiation Effects in Photonic Integrated Circuits
Adrian Ildefonso (Indiana University)
Photonic Integrated Circuits (PICs) are emerging as compact, efficient solutions for space-based communications, sensing, and navigation. As these technologies advance toward flight applications, understanding their response to radiation is increasingly important. This tutorial presents an overview of radiation effects on PICs, including total ionizing dose, displacement damage, and single-event effects. It examines how radiation impacts key components and summarizes recent experimental findings. Testing approaches and considerations relevant to space deployment will also be introduced.
Dr. Adrian Ildefonso is an Assistant Professor of Intelligent Systems Engineering at Indiana University Bloomington. He received a B.S. in Computer Engineering from the University of Puerto Rico at Mayagüez in 2014 and an M.S. and Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2017 and 2020, respectively. Before joining Indiana University, he was a research engineer and a Jerome and Isabella Karle Fellow at the U.S. Naval Research Laboratory in Washington, D.C., where he developed laser-based techniques to emulate radiation effects in microelectronic devices.
Dr. Ildefonso’s research focuses on radiation effects and reliability in advanced microelectronic and photonic systems, with an emphasis on laser-based single-event testing, radiation-hardness assurance, and predictive modeling of device behavior in extreme environments. He has published over 50 peer-reviewed journal articles and received several best paper awards. He is a Senior Member of the IEEE and the recipient of the 2024 Radiation Effects Early Achievement Award from the IEEE Nuclear and Plasma Sciences Society.
TUT12: Thermomigration in Advanced Interconnect
Olalla Varela Pedreira (IMEC)
TUT13: MOL/CPI Reliability with Application Specifics
Patrick Justison (GlobalFoundries)
TUT14: 3D-NAND Scaling and Reliability Challenges
Yoshiaki Fukuzumi (Micron Technology)
3D-NAND Flash Memory has been continuing bit density scaling of 36% annually, resulting in 30-fold increase over the past decade. With the advent of the AI era, the demand for scaling of bit density, performance, and cost are becoming even more stringent. This tutorial will begin with a brief overview of NAND Flash fundamentals, followed by a history and future outlook on 3D-NAND scaling. Additionally, it will address the reliability challenges that accompany these advancements.
Yoshiaki Fukuzumi received his B.S. and M.S. degrees in Applied Physics from the University of Tokyo, Japan, in 1994 and 1996, respectively. He began his career at Toshiba, where he worked on device and process development for DRAM, Floating-Body Cell, and MRAM technologies. Following his research on resistive RAM as a visiting scholar at Stanford University, California, he started the development of 3D Flash memory in 2006 and led the device and process development of 64-layer NAND project.
He joined Micron Technology in 2018 and currently serves as a Fellow in Advanced NAND Technology, leading the NAND technology team in Japan. His work focuses on NAND technology pathfinding, including cell device innovation, array architecture exploration, and process integration strategies to enable continued scaling in cost and performance.
TUT15: BTI Reliability in CMOS Technologies: Degradation Physics, Process interactions, and Modeling Challenges
Narendra Parihar (Intel)
Bias Temperature Instability (BTI) aging in CMOS transistors—particularly Negative BTI (NBTI) in PMOS—remains a major reliability challenge as the industry advances toward gate-all-around technologies. This tutorial provides a detailed exploration of BTI fundamentals and degradation mechanisms, focusing on how process integration choices, material properties, and device scaling modulate BTI effects. We review state-of-the-art modeling methodologies, addressing time, voltage, and temperature dependencies, and present acceleration and extrapolation strategies to ensure accurate long-term device and circuit reliability.
Dr. Narendra Parihar earned his Ph.D. in Electrical Engineering from the Indian Institute of Technology Bombay in 2018. In 2019, he joined IMEC, Belgium, as a device researcher, focusing on advanced CMOS device engineering. He has authored more than 40 publications in peer-reviewed journals and international conferences, and has contributed to multiple book chapters. Dr. Parihar has actively served on the technical program committees of several IEEE conferences. Since 2022, he has been part of Intel’s Foundry Quality and Reliability Pathfinding team, where his work centers on advancing front-end reliability modeling for Intel’s cutting-edge technologies.
TUT16: Fundatmental Reliability Challeges for OFETs
Chadwin Young (University of Texas at Dallas)
TUT17: Application of Physics of Failure and Degradation in Extended Mission Profile Assessments
Rene Rongen (NXP)
On the journey towards autonomous vehicles, smart factories, and robotics-driven automation, semiconductor content in these complex systems is increasing rapidly. Cars, industrial equipment, and consumer applications with the latest advances today, will be antiquated tomorrow.
This accelerated innovation cycle introduces new reliability challenges. Traditionally, reliability research focusses on Physics-of-Failure, understanding failure mechanisms to improve reliability margin. However, the paradigm is shifting towards Physics-of-Degradation, which emphasizes monitoring and evaluating the gradual deterioration of components and systems.
René Rongen is a Fellow in Applied Reliability at NXP. Since joining Philips/NXP in 1997, he has built deep expertise in reliability physics, contributing across a wide range of technical and strategic roles. René plays a central role in shaping NXP’s reliability practices. He is the lead editor of the company’s Reliability Policy, owner of key product reliability test specifications, and the NXP Reliability Knowledge Framework. His influence extends beyond NXP through active participation in global standardization bodies such as AEC, JEDEC, and ZVEI.
Next to Vice-Chair of AEC, René is instrumental in the development and revision of key industry standards, including AEC-Q100, AEC-Q006, JESD47, and the ZVEI Handbook for Robustness Validation. His work helps ensure reliable, high-quality semiconductor products across the electronics industries.
René is also a contributor to the technical reliability community. He has (co-)authored numerous papers on Cu-wire reliability, solder joint performance, challenges wafer-level CSP devices and lately electric parameter drift due to package aging. He is active at leading conferences—including IRPS, ESREF, ECTC, and the AEC Reliability Workshop—as a speaker, paper presenter, and technical committee member. In 2023 and 2025 he chaired the AEC Reliability Workshop under the umbrella of the ESREF conference.
From 2005 to 2018, René supported the Dutch Accreditation Council as a reliability test specialist, contributing to the ISO/IEC 17025 accreditation of reliability laboratories across the Netherlands.
TUT18: Journey with AI for Accelerating Reliability Estimation from Transistors to GDS
Hussam Amrouch (Technical University of Munich)
This tutorial will demonstrate how machine learning and deep learning techniques can significantly accelerate reliability analysis across the entire design stack—from TCAD simulations to the final GDS level of advanced chips. We will highlight how aging-induced degradations and self-heating effects can be modeled and estimated with high accuracy at the GDS level, even for highly complex designs such as full processors under workload-induced activities and advanced AI accelerator IPs.
Hussam Amoruch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM), Germany. He is also the head of Brain-inspired Computing at the Munich Institute of Robotics. Further, he is the head of the Semiconductor Test and Reliability department at the University of Stuttgart, Germany. He is also the Academic Director of TUM Venture for Semicondcutor. He is also Fouding Director of the Munich Advanced-Technology Center for AI Chips. He received his Ph.D. degree with the highest distinction (summa cum laude) from KIT, Germany in 2015. He has over 310 publications (including over 125 articles in many top journals) in multidisciplinary research areas covering semiconductor device physics, circuit design and computer architecture. His research interest is design for reliability, AI acceleration, emerging technologies, in-memory computing, and cryogenic circuits . His research in AI chips and reliability have been funded by the German Research Foundation, Bavarian ministry of economy, Bavarian ministry of science, Advantest Corporation, and EU.
TUT19: Bias Temperature Instabilityin BEOL-Compatible Oxide Semiconductor Transistorsfor Ultra-High-Density Monolithic 3D Ics
Xiao Gong (National University of Singapore)
TUT20: FeRAM
Kai Ni (Notre Dame University)
TUT21: SRAM HTOL Reliability
Yuncheng Song (IBM)
TUT22: Challenges in Gate Stack Integration, Defectivity, and Reliability of 2D Material FETs
Quentin Smets (IMEC)
Two-dimensional (2D) materials, particularly Transition Metal Dichalcogenides (TMDCs) offer new opportunities for CMOS scaling due to their atomic thinness, self-passivated nature and van der Waals interfaces. Yet, these features introduce critical challenges for gate stack integration and defect control. This tutorial reviews gate stack integration and dielectric deposition approaches, defectivity and reliability characterization techniques, and outlines benchmarking strategies essential for assessing process maturity towards industrial adoption of 2D FET technology.
Quentin Smets is a Senior Researcher at imec (Leuven, Belgium), specializing in field effect transistors with 2D material channels. He received his M.Sc. and Ph.D. degrees in Electrical Engineering from KU Leuven, where he investigated tunnel FETs with III-V semiconductors. He now leads efforts to bring semiconducting 2D materials into a CMOS-compatible 300 mm production flow. His work focuses on novel modules for channel, gate stack, and contacts, implemented in imec’s 300 mm pilot line. As device engineer, he develops the electrical characterization methodology and investigates device performance, scaling, variability, and reliability. He has authored and co-authored multiple publications in leading journals and conferences, including IEDM and VLSI.